There is a need in the art for high power, high density interconnects for integrated circuits. Current generations of supercomputers, such as those built by Cray Research, Inc., the Assignee of the present invention, use integrated circuits that are very fast, very dense, and require large quantities of power. Such integrated circuits often contain hundreds of I/O connections, and as a result, their carriers have extremely tight lead spacing that allows little room on printed circuit boards for crossovers and interconnections. In addition, as clock speeds increase, the length of electrical interconnects must become shorter.
In the prior art, integrated circuits are typically mounted on single or double sided and multi-layer printed circuit boards. Multi-layer boards normally include ground planes interspersed between the signal layers to minimize noise and to provide a controlled impedance of the signal lines. However, prior art manufacturing techniques for printed circuit boards do not provide ideal solutions to the problems of lead spacing, line widths, impedance control, etc., required for dense, high-speed, high-power integrated circuits.
Standard printed circuit board technologies suffer from several disadvantages. Vias are typically drilled through the printed circuit boards and thus cannot be constructed with the appropriate sizes. In addition, it is difficult to start and end drilled vias at the correct spot.
Thin film technologies also suffer from several disadvantages. Thin film cannot provide the necessary metallization thickness needed for dense, high-speed, high-power integrated circuits. Thin film metallization also suffers from unacceptable DC voltage drops when extended over a distance.